1. Field of the Invention
This invention relates to the formation of an isolation region in the substrate of an integrated circuit structure. More particularly, this invention relates to a method for forming such an isolation region in which a layer of epitaxially grown material is formed over an isolation slot formed in the substrate of an integrated circuit structure, thereby eliminating the need for a separate step to refill the slot after the slot walls have been oxidized.
2. Description of the Related Art
In the construction of integrated circuit structures, isolation regions are formed to electrically isolate and insulate adjacent active devices, or components, from one another. One such method for forming such isolation regions involves the formation of a slot or groove in a substrate. The walls of this slot or groove are then oxidized, to form the desired isolation or insulation, followed by refilling of the slot, usually with oxide or polysilicon. The surface of the structure is then planarized using wet or dry etching techniques and/or mechanical polishing.
While such methods do result in the formation of isolation regions which effectively insulate/ isolate active devices and components from one another, damage to the substrate can occur during the processing steps used in forming the isolation region.
For example, damage to the substrate may occur due to stresses formed by excessive oxide growth in the slot. The substrate may also be stressed by void formation during refilling with polysilicon as a result of opening the void during subsequent planarization followed by oxidation of the sidewalls of the void. Formation of an oxide cap on the slot, in a manner wherein the oxide grows down into the slot, can also create stress. Mechanical polishing of the structure during planarization after refill may break the wafers, or leave refill material on the backside of the wafers which may also warp the wafers.
It would, therefore, be desirable to provide a method for forming an isolation region in the substrate of an integrated circuit structure while inhibiting or eliminating the formation of damaging stresses in the crystal structure of the substrate during such processing.